PCB Assembly Services - Screaming Circuits: Via Current Capacity


Via Current Capacity

Over on the Circuits Assembly blog, Michael asked a question about my Via in Pad Myth #5. He asked:

"I have a question about vias. I have seen charts on the current carrying capacity of traces, but what about vias?"

That's a good question. I've heard that you first need to know the thickness of the via wall. Then, once you know that, you can calculate the trace-width equivalent for the via by using the formula for the circumference (diameter X pi ). For whatever number that gives you, compare the closest smaller trace width.

Via cross section My related questions to all of you PCB fabrication gurus out there are:

Since vias are not created in the same way as the trace plating is, can that simple formula be used? While the trace copper is laminated onto a nice smooth PCB surface, the vias are typically created by deposition of copper dust in the via and then electroplating more copper. Then the surface finish is applied to all of the exposed metal. The via walls would generally be rougher than the flat substrate surface. Does that have an impact on the current capacity of a via?

Further, since airflow will be somewhat restricted in a via relative to a surface, should the via effective width be compared to an internal trace instead of an exposed surface trace? Should it be a compromise between the two?

If you look closely at this via cross I pulled from Wikipedia, you can see that the via wall looks to be thinner that the traces. You'll have to make sure that your board fab house can give you an accurate thickness of the via wall.

Duane Benson
If you know the via current capacity, can you calculate the past and future capacity?


TrackBack URL for this entry:

Listed below are links to weblogs that reference Via Current Capacity:


In normal cases the via is able to carry much more current than the trace (if they are relatively close in size - like a building engineer who always just calculates the strength of the materials, not of their connections as these have always to be much stronger). Just don't place a via in the middle of your trace as that would create a weak spot. As generally the rim is the critical place. Make sure half of the current can enter the via from the rear (wide enough rim at both layers). Also take any thermo-traps (or how that's called in English) into consideration. It's no good to make a wide trace and large pin hole and then have it end in a ground plane with thermo-traps enabled - just 4 very thin traces of copper instead of a full ring. Otherwise - if the trace can take the current the via can too (general rule of thumb of course). My comment is based on some study of how current moves through a via which I read 20 years ago (yeah, current still moves the same ways as it did 500 years ago, don't worry).

For 10mil dia you are quoting 1.12amps but i got 1.83 amp a difference of .7 Amps in comparison to few other online calculators like saturn.
Can please help me uderstand how did you arrive at the value.
I have considered same factors quoted above.

I'm not sure if anyone is going to read this, but via current cannot be calculated the same way as traces. The plating does not create a uniform thickness for the via barrel.
Here are some numbers for 25degC temp rise, k=0.024, and 1mil plating minimum.
Drill Hole Size(mil) - Amps
10 - 1.12
15 - 1.54
20 - 1.92
25 - 2.27
30 - 2.61
35 - 2.92
40 - 3.23
50 - 3.81
60 - 4.36
Hope that helps somebody

Cooling towers are an essential element in any large scale industrial activity recently. Due to the growing need of cooling towers around the world and in India in particular, many companies have been set up to meet the demand of such towers in various industrial applications.

Hey, I saw this post a few days ago, and I happened to be building a PCB at the moment. So, I stuck a few test vias in to check their impedance. I used a 4-wire technique, where I run current through one pair of wires, and measure the voltage with the other pair.

I only measured 1 board so far, so i don't have any error bars on my measurements.

Board specs: 6-layer, vias don't connect on inner layers. Manufactured by siera proto express, using their 'no touch' process.

Diameter : Impedance
10mil : 0.50 mOhm
12mil : 0.44 mOhm
15mil : 0.29 mOhm
20mil : 0.24 mOhm

I'm sure there are real studies on via impedance, but I figured I'd give this a quick check on the process I used. Maybe not totally useless data :-)


Post a comment

If you have a TypeKey or TypePad account, please Sign In.

« Via-In-Pad Myth #5.A | Main | Favorites »