QFP/SOIC/SSOP Mechanical Security

I've written a lot about QFN footprint issues, but the venerable old leaded SMT configuration is still around. It gets its share of disrespect and questionable footprints too. When you give it a post-solder visual QFP fillet inspection, mostly what you see is the fillet "B" in my illustration. But, here's a question: which fillet is more important, A or B? The hidden fillet, A actually gives more of the mechanical strength then does B.

Most CAD library parts will have the proper footprint for these parts, but not all. Sometimes you have something close, but not exact. If that's the case, make sure the pad leaves room for a good fillet on both sides of the lead. Doing so will ensure that you have the best mechanical connection. Don't use red solder though. It might actually be Play-dough and Play-dough isn't a good conductor.

Duane Benson
Silly Putty won't work either

Package on Package Layout

Amkor POP sm Last week in one of my Beagleboard posts, I was musing on the issues related to layout with a package-on-package form factor. I pondered a couple of options, but Occam's Razor held true. Gerald Coley, the designer of the BeagleBoard pointed out that the CAD software simply doesn't care. And that's perfectly logical.

If you're designing with POP like the Ti OMAP processor, just don't worry Beagle-smabout it. There are no layout issues - except for all of the normal ones like escape routing, trace current capacity, crosstalk, components spacing, vias in pads, etc, etc. Just place the bottom part where it's supposed to be, like you would if it isn't POP.

The manufacturing folks, on the other hand, do care. But that's easy. Just put the POP top part at the same XYtheta location in the centroid (pick and place) file and make sure the build instructions are clear that it is a POP part. Simple.

Duane Benson
Curse you Red Baron!

Moleish SMT Heatsinks

Little-moleWell, no one ever did give me a reasonable estimation at how deep a mole of moles would cover the  earth. But then, I didn't go back and dig up my old chemistry notes and see if I could find my calculations from nigh on eighty years ago either. Nor did I get out my old Handbook of Chemistry and Physics and try to recreate the calculations from scratch. Maybe I didn't give enough information or parameters for the question - like, just what kind of mole are we talking about here?

Anyway... back to something you might actually care about... D2Pak-w-heatsink-copperI ran across some writing about thermal vias and big parts the other day. Not that the material had anything to do with Avogadro - except maybe that sometimes it looks like a board will have a mole of via holes on the thermal pad in an attempt to get heat away from a power part. If done properly (filled and plated over), that can be a viable option.

For some chips there may be other options too though. A couple of companies make SMT placeable heat sinks for D2Pak and similar chips. I haven't personally used any of these, so I can't speak to the performance, but AAVID and Wakefield are two examples.

The basic idea is that you make the thermal pad a little bit wider, put a small strip of solder mask in between the part and the heatsink spot and you won't need an vias. Look at the heatsink data sheet specs to get the exact dimensions of everything. You'll end up with a part footprint that looks something like this one.

The cross hatch area represents bare copper (or whatever board surface you are using) and the rest would have solder mask. The thin layer of mask between the part and the heatsink will help to ensure that you have better control over the amount of solder under the part and the sink. It should also help prevent solder balls as well.

Duane Benson
How about gophers?

Very Compact Layout?

How do you do it? We've told you not to space things too close. We've told you not to put vias in pads - like a million times. We've told you to watch out for spurious vacuum tubes. Okay, the last one doesn't really count. Vacuum tubes put off a lot of heat and you won't find many with .5mm or less lead spacing so compactness isn't so much of an issue as it can be with mobile devices. Although, I haveTight tubes seen some pretty tightly packed tube designs from the '60s.

Anyway, say you're trying to put a little intelligence into a tiny little package and you just don't have space to route around here and there. Your parts are too close for anything more then maybe a single trace or two between parts.

Here is where the infamous via-in-pad, like Under-dog, can arrive to save the day. We ran across a project a while back with no visible traces on either surface of the board. That technique's actually showing up more and more often with dense-pack designs. All of the traces are on inner layers. It looks pretty weird, but it works very well - if done right.

Before assembly, there also weren't any visible vias. Not a one. All of the components, including Packed in tight passives did have vias - every connection was though a via (via a via???). However, all of the vias were properly filled and plated over at the board house.

So, if you need a 0.52" x 0.42" microcontroller / motor driver like this one, go ahead and give it a shot. Just make sure you fill and plate your vias, and you can use them liberally.

Also make sure you don't interfere with thermal requirements, though. I still have to move the parts out from under the thermal pad of the A3901 motor driver and the little 0201 out from under the thermal area under the MCP1726 regulator here. The PIC doesn't generate enough heat to worry about, so that underside area is fair game.

Duane Benson
Tiptoe through the 0201's with me

Non Solder Mask Defined pads on BGAs

OSP NSMD bga pads The industry generally recommends NSMD (non solder mask defined) pads on BGAs and so do we. There are some exceptions though. When you get into really small ball pitch, you probably need solder mask defined pads to help prevent bridging. See this post here.

This photo does a good job of showing NSMD pads up close and personal. The registration could be a bit better, but this isn't too bad. There's a nice small gap around the pad with no mask up on the copper.

You'll also notice that there's a good bit of solder mask between the pad and the escape via. That's also good practice. And, of course, no vias in these pads.

You can put vias in the pads, but if you do, you really want them filled and plated over. Never, never, never put an open via in a BGA pad. There are plenty of options at the board house for filling and plating these days.

Duane Benson
I hope NSMD doesn't mean "Never Send Money to Duane"

Land Patterns and Component Spacing

One of the biggest causes of challenges with assembly these days seems to be component spacing, as I wrote about here.

We reference IPC spacing guidelines from time to time. Like, we'll say: "use IPC spacing guidelines" and stuff. That's all fine and good - unless you don't know where to go to find the IPC IPC LP viewer component spacing guidelines.

IPC-7351 is one of the things you're looking for. The IPC even has a handy dandy piece of software that you can download here at ipc.org or here and PCB Matrix.

I'm not sure how current their libraries are and if they have super new things like I covered in this post or this one, but I'm sure you can use similar parts to get pretty close to good spacing.

If you can't figure it out from there, a 20 mil courtyard is generally a pretty good rule of thumb.

Duane Benson
The best way to find something is to actually look for it.

Keep Out Area 51

According to the glossary on the Maxim website, a "Keep-out zone/area" is defined as:

"The area on or near a CPU or GPU processor that the circuit board layout design can not use, due to thermal management components, cooling, and mounting constraints."

In the efforts to shrink boards down or get the bypass caps closer to high speed parts, it's becoming more and more common to see components located closer and closer together. This is all good up to a point.

Sometimes, it's obvious because the two components just don't fit, as in the close up of the TO-220 andKeepout actual overlap capacitor here. Sometimes, though, it's not so obvious. Violating spacing rules may lead to solder bridges or thermal problems, not to mention mechanical troubles.

Many, but not all, CAD library footprints have a keep-out area specified in addition to all of the other layers. Well, in theory, they should have the keep-our area specified. I bet most don't though.

Keepout areas On the caps in the PCB drawing here, the outer red box is the keep-out zone. Nothing should be in there except the trace going to the part. You might possibly actually be able to place all the parts on this little board, but there are several spots likely to get bridges or have component interferences. Regardless, you could not expect this example to be reliably manufactured anywhere by any method.

Too tight component spacing is one of the most common issues we're seeing these days. I know you need to keep the board small, but for a reliable assembly, respect those keep-out areas and get out your IPC book if you have any spacing questions.

BONUS POINTS: I have a lot of parts spacing issues in the little CAD drawing as well as some other boneheaded moves. The first readers to point out each of the three other big mistakes will get a 10% discount code for use on your next assembly order. Email your answers to me at: dbenson@screamingcircuits.com.

Duane Benson
Everybody was kung foo fighting
Those kicks were fast as lightning...
I don't know why, but I've got that song stuck in my head. Ugh.

0.4mm pitch BGA pads

At 0.5mm pitch and larger, we generally recommend non-solder mask defined (NSMD) pads for BGAs. The NSMD pad will allow for better adhesion with the solder being able to grip the sides of the copper in addition to the top surface. Even down to 0.5mm pitch BGAs, most part manufacturers still say to go with NSMD pads. Granted, you need to make sure your fab house can do a good job of mask registration. It's no good to have pads that are half SMD and half NSMD. We've seen that.

Once you go down to 0.4mm pitch BGAs, though, things get different. We're starting to see more and more of these. Some CSP (chip scale package) or WSP (wafer scale package) BGA and LGA parts are starting to show up in 0.4mm pitch, as well as some bigger parts like the Ti OMAP processor.

At that size, you start to see more risk of solder bridging with NSMD pads, as in the left side of the illustration below.
0.4mm pitch SMD BGA pads 
This is a somewhat exaggerated view, but it shows the potential problem here. With such small geometries, you probably aren't going to be able to route escape traces on the top layer either. You'll have to put blind vias in the pads and escape through the inner layers. By the way - NO OPEN VIAS IN PADS. The pad needs to be solid metal with such a part. No exceptions. Don't try using solder mask to cap the vias at this pitch either. Plate over it. It has to be all metal.

You can finds some more detail here in a design guide written by Ti for their OMAP processor. Pages 8 through 12 talk about pads, mask and vias. Obviously, you should consult similar materials written specifically for the part you are using, but Ti did a great job of covering all the issues here so I use it as a good general piece.

Duane Benson
Are you there Moles? It's Edgar.

And Another Reason...

Another reason to inspect your PCBs before sending them on to the assembly house.

Missing barrel 

At first glance, these boards looked fine. But with a little closer inspection, you can see that the middle barrel isn't plated through. Bummer.

There are a number of possible causes for this.

  1. It could simply have been a goof at the board house. Sometimes a process will slip or someone in CAM will introduce an error.
  2. It could have been caused by improperly creating a library part. Maybe the symbol was built up by hand and ended up with a non-plated hole in that spot.
  3. It could have been built without a library part. Sometimes designers will just create a place for a thru-hole part using vias and traces instead of creating the library part. If that's the case, the center could have ended up with a non-plated hole instead of a plated via.

Myself, I'm betting this was a board fab problem. In any case - another good reason to check out those boards before sending them on for assembly.

And even better then just looking at them - also have them electrical tested at the fab house. Our fab partners at Sunstone Circuits can do that for you.

Duane Benson
Roll out the barrel...
and have a barrel of open solder joints

Oxidized Silver? What do you do???

I've written before about the shelf life of immersion silver PCBs. In that post, I alluded to the possibility of carefully cleaning an oxidized immersion silver pcb but I didn't say how to do it. Sometimes an oxidized board can be cleaned. Sometimes it can't.

Their are really only two industry recommended practices:

  1. Send the boards back to the fab house to have them re-plated
  2. Get new boards if re-plating is too expensive

That being said, you can sometimes use a large rubber eraser to clean them. It's easy to mess the boards up though so it won't always work. I would not do that in a production environment or with an expensive board. And it won't do anything for plated through holes for thru-hole parts. For that, you'll need to go back to your board house.

Here's what one of our engineers said about the process:

"The problem with immersion finishes, silver in this case, is that the oxidation or tarnish is the remaining oxide/sulfide/sulfate/chloride compound (depending on what's in the area to react with) conversion of original silver content. The immersion coating is so thin to begin with, cleaning away the tarnish would basically leave you with little to no silver and the undercoat (usually nickel) exposed. Also, the type of tarnish/contamination is a big factor. The sulfur compounds (sulfide/sulfate) are worse - i.e. cause more solderability problems, then the oxide/chloride compounds. I'm not a chemist, so don't ask why.... :) Of course, the only way to find out what particular type of contamination is most prevalent on a give board is to have it analyzed.... Probably cheaper to get new boards!"

I've heard about some studies at Sandia National Labs regarding the life and solderability of tarnished silver boards. I'll try to look that up and if I can find it, I'll post some notes about it.

Duane Benson
sulfide, sulfate
sulfide, sulfate
Swiftly fly the years
One season following another
Laden with happiness and tears