Screaming Circuits: Tips and tools


Pads on Ground Plane

Pour-no thermalGenerally, small pads for passive parts are connected  with a single PCB trace of equal size to each pad. That's the right way to do it.

However, sometimes, circumstances dictate a little different approach. The illustration on the upper right here shows something of a worst-case. This is for a snubber (resistor, capacitor pair) between two power planes.

A couple of things will likely happen. The power plane will act as a heat sink, preventing the solder paste on one side from melting, resulting in a poor connection. Or, the unequal melting could lead to surface tension pulling the part up, causing tombstoning.

Pour-with thermalMost designers are aware of that, but sometimes, thermals will be deliberately turned off to allow for better current capacity to and from the large power Mosfets (not shown). If that's the case, make sure that you can turn the thermals (see image on loer right) on or off by the part, rather than just by the plane.

Duane Benson
The rain falls mostly on the ground plane due to static attraction

10th Anniversary Top 10 Traps

A few folks requested my presentation from out 10th anniversary open house.So, without much adieu, here it is.

Download Top 10 traps 7-2013 (PowerPoint format)

Download Top 10 traps 7-2013 (PDF format)

Duane Benson
10 times 10 isn't necessarily equal to 10 times 10.
Especially if you mix bases.

Super Small Via In Pad

Via in pad is an old issue that still pops up now and then. Our standard answer hasn't changed: No open vias in pads. But one of the questions we get related to the subject is: "What if we make the vias really small?"

Beagleboard U6 viasLogically, that makes sense. In fact, in some cases, the via is so small that it's essentially closed. If it's so small that it really is closed, then it's not an open via. But look close - if it's closed with solder, that solder may melt during reflow leading to an open via.

The images here show some pretty small vias. I believe they're 0.3 mm in diameter.

Beagleboard vias back sideIn the first picture, on the left, it appears that the vias are open. They aren't though. This board (an unstuffed Beagleboard) uses soldermask on the back side of the PCB to close off the vias, as shown in the image on the right.

Our recommended method (se more detail here and here) is to plug the via with copper or epoxy and have it plated over at the board fab house. Next, we'd recommend via caps on the component side. FInally, capping the back side with soldermask, like this example can work, but it comes with the risk of voids. The via caps and also pop open, leading to an open via.

Duane Benson
No more open vias-in-pad, I mean it!
Anybody want a peanit?

Push-me Pull-you LEDs

I may never get tired of talking about LED and diode polarities. It's so much fun. Not long ago, I wrote about two LEDs from the same manufacturer, marked with opposite polarities. I recently ran into another one, but at least this one tells you on the same datasheet. This image is an actual unmodified clip from the datasheet.

LED confusing polarityI can't for the life of me understand why this would be done on purpose. I could maybe understand is one was designed in a different building, but it couldn't have been too hard for someone to say: "Hey - wait a minute..." before sending these things off to manufacturing.

Of course, maybe they built a million before noticing and then just decided it would be easier to change the datasheet. Regardless, it's kind of nuts in my opinion.

The other thing here is that, while you can generally get away with the indicators "+/-" on an LED, you can't with all diodes. Thin Zener and TVS.

Duane Benson
Matter + antimatter makes what?
Does it really matter?
Does anybody really know what time it is?

LEDs - Seeing Double

Dual LEDLike I do so often, I'm being a bit redundant. While I'm all for stamping out and eliminating redundancy, this is redundancy with a purpose (not a porpoise). Not long ago, in a galaxy not far away, I blogged about annoyances in surface mount diode polarity markings. You can read that here.

I'll wait.

Messy isn't it? Well, after reading that blog, someone asked me about dual diodes. For some reason, I can't seem to find the page covering dual diodes in my IPC book, but that's not the important part. What is important is the way the diodes are marked on the PC board.

We do ask for centroid data which, in theory, contains the component rotation. That would be cool except that we find that far too often, the zero degree orientation (and the rotation from that) differs from the standard. That, and there are seemingly half a dozen or so standards.

Since LEDs don't work too well backwards, we really would like to see everything marked in a non-ambiguous way in silk screen (or in an assembly drawing if you don't have silk screen). A "cathode bar" won't work because it could be a bar indicating the cathode or negative. The cathode isn't always negative, especially when looking at TVS or Zener diodes.

Mimicking the diode markation pattern printed on the part may not be secure either. Read that article I linked to right at the start of this blog. What if you put silkscreen down to match one of those LEDs but ended up buying the other one? That's exactly what I did myself. Trust me. It just leads to disappointment and possible soldering iron induced finger burns.

So what is the answer, and why am I talking about single LEDs and TVS diodes when the blog is about dual LEDs? Well, the answer is the same. The best way to communicate the desired polarity of an LED or any kind of diode is with a mini version of the schematic symbol. It doesn't matter if it's a single LED, dual LED, Schottky, Zener or what ever kind of diode. The schematic symbol is the clearest way to go.

Led marking

The diode footprint has the manufacturer's polarity marking, but I don't care. I still put the diode schematic symbol next to it. If you don't have room for silk screen, put it in an assembly drawing. You won't regret it.

Duane Benson
And they called him Flipper...

Creating a QFN Footprint - the center pad

I've written bits and pieces about creating footprints in Eagle and a lot about what the QFN solder paste layer should look like, so maybe it's time to connect the two dots. I'm using Eagle CAD here, so your process will likely be different unless you're using Eagle, but the concept should be the same. This process takes place in the package section of the Library editor. I'm assuming that you're already part way through and just need to put in the center pad.

Center pad Center pad position and sizeFirst, add the center pad to your QFN using the "Smd" tool and set the size based on the recommended pad size specified in your part datasheet.

The center of the pad should be located at 0,0 unless you have a QFN with odd shaped or multiple pads.

Make sure you un check the "Cream" box in the lower left corner as we'll be doing that manually.

After the pad is there and sized right, you need to add in the cream (solder paste) layer. You'll be drawing the cut-outs in the stencil with the rectangle tool. Use the rectangle tool to draw the stencil cut-outs. Set the rectangle to the "Cream" layer. In my installation of Eagle, the Cream layer defaults to layer 31.

Most parts should get 50 - 75% paste coverage to prevent floating (read this for more details). If your Stencil rectangle Stencil rectangle position and sizepart datasheet gives a specific number, use that. However, in my experience, most part datasheets just show a wide open stencil with 100% paste coverage. Unless you have good reason, don't do that.

Without any specific guidance, I usually aim for about 70%. In high volume manufacturing situations, the manufacturing engineers will likely spend time tweaking the coverage, but it'll be close and for a prototype, 70% is a good number.

Duane Benson

Will a Via Fit Between?

I don't know that it would be accurate to say that BGA's have ever been easy, but with 0.4mm pitch being common and 0.3mm pitch showing up, some of the older size, like a WHOLE millimeter pitch seem 0.5mm pitch padspositively spacious. With 1mm and larger ball pitch, putting a via between the pads (not in the pads) is a no-brainer.

IPC-7095B classifies 0.8mm and smaller pitch as fine-pitch. It really starts to get complicated at around that point. For example, take a 0.5mm pitch BGA. Since we're looking to put a via between the pads, the diagonal pitch is the critical measurement. In this case, it's 0.71mm (17 mil). It might immediately seem like that's plenty of room for a 6 mil via, but upon closer examination, not so much.

0.5mm pitch pads viasIPC states that a 0.5mm pitch BGA will have a nominal pad diameter of 0.3 mm. It should be a non-soldermask defined pad, which will add about 0.07 mm to the pad diameter. That gives 0.44 mm total pad diameter. The radius is 0.22 mm (8 mil). Take that out of the 0.35 mm (14 mil) you have to work with and you're not left with much space.

If your fab house can do 3 mil trace and space, you will end up with enough room for a 0.06mm (5 mil) via, including annular ring. That's not much space. Most designers, at that point, will seriously consider putting the via in the land pad and having it filled and plated over. You can't leave the via open or un plated.

Duane Benson
All was in chaos, 'till Euclid arose and made order

 

Via in Pad x 8

Via in 8 pin padsHere's an interesting via in pad case. On the one hand, the footprint is very symmetrical and clean looking. On the other hand, it has open vias in the pads.

At first glance, I thought this was a DIP footprint with extra long pads, but it's not. It's for an SMT part. Personally, I would have put mask between the pads. Looking at the rest of the board (not shown), the spacing between pads and mask is pretty wide, so there may be a good reason. I'm not sure though.

Definitely, though, I would not put the vias in the pads like that. Those open vias will cause solder to flow down to the other side of the board, make a mess there and leave the chips without sufficient solder.

Duane Benson
Sucking solder through a straw - or via

More Thermal Examples

Speaking of thermal relief... Here's an interesting example I ran across the other day.

Thermal relief can be a pain. If you've got a high current device, you may want more than just the thin little connections, one per side, that you get with thermals. You might feel the need for greater current capacity or you may need all the copper to distribute heat. You might have one pad, like in this image, that lands on a plane but not the other one.

In this particular board, the designer just made a few parallel traces coming out of the pad rather than one thick one.

Multi-via passive

The other side of this passive part sits right on the ground plane and has the standard thermals so the other reason this might have been done is to keep the amount of copper trace coming into the pad to be equal to that on the other side. It doesn't have exactly the same amount of copper going into both pads, but it's much close than if just one thin trace had been connected on the left pad.

Duane Benson
One thin trace rides away

Electrolytic Ambiguity

I've written about ambiguity a few times before, like this post about fiducials. But I'm not talking about the PC board today. I'm talking parts. More specifically, I'm talking about silk screen markings for your parts on the PCB.

CapacitorsDiodes have a lot of opportunity for ambiguity, as you can read here. There are many ways to mark parts, but fewer ways to clearly mark them. Take a typical electrolytic capacitor. It can be thru-hole, smt metal can, tantalum, or a few other form factors. The capacitor manufacturers aren't doing any of us any favors where markation is concerned.

Check out this image. Yikes! In all cases shown here, I've oriented positive on the left, which, according to IPC is pin 1. This is also the zero degree rotation for the centroid value. But, isn't it nice of those component manufacturers to put the identification bar on the positive side for tantalum capacitors and on the negative side for metal can electrolytics? Not!

So, how should you mark this in the silk screen on your PCB? For an electrolytic capacitor, the best approach is to mark the positive sided with a (+), plus sign. If you mark pin 1, with the number 1, it can easily be mistaken for the minus sign. If you mark the negative side with a minus sign, it can easily be mistaken for pin 1.

For a metal can capacitor, it is also acceptable to put the notched outline in silk screen. We still recommend that you place the (+) plus sign on there too.

Duane Benson
I'm just positive I put the negative right on the left