Screaming Circuits: QFN and DFN

QFN / QFP switcheroo

Here's an all too familiar face. We see this a lot with chips that have both a QFP (quad flat pack)and a QFN (quad flat pack, no leads) package. Especially if the QFP packaged part has been around for a long time and the QFN version is fairly new.

Qfp_qfn_4 In the CAD package, the two components look pretty close. You have a center flag pad and lots of leads. Unless you have the component sitting right there with you, it's not always easy to tell at a glance that you have selected the wrong package. A quick give-away though is the length of the leads. If you have long lands for the leads like this footprint, it's a good bet that you have a QFP library part. I won't guarantee it, but it's likely enough that you should conduct some further investigation to make sure you won't end up with sad boards like these.

The reverse is true too. If your actual component is a QFP and the land pattern has very short leads, you should look closer.

Duane Benson
Quirky perhaps Mr Longfellow

Good QFN, Good QFN Paste Layer

Qfn_package_sm_2I write a lot here about things that go wrong with various layouts. Hopefully by doing that, I can help some of you avoid common pitfalls. But I should probably write about more good things though to balance it out.

So, here's a decent example. This is a good way to specify the solder paste layer for Good_qfn_stencil_c_2 your QFN parts. Notice that the center thermal area is segmented to give about 50% paste coverage. This will lead to a secure and reliable placement with minimal voiding underneath.

Good_qn_before_pasteThere are a lot of different ways to segment the stencil for good paste coverage. This is one is easy to do and will work well. Note that this QFN doesn't have any thermal vias so here we don't have to worry about any via in pad issues. If you do need thermal or grounding vias in the pad, check out our section on via-in-pad for guidelines to help properly deal with the.

Duane Benson
All we are is paste on the pcb
Just a drop of solder on an endless stencil

Parts Library Strikes Again

Here's a little bit of a parts library or wrong package problem. I'm not exactly sure how it happened. The Qfn_worng_part_library_2 board may have been laid out for a small QFP footprint but then a QFN part was purchased. The footprint looks like that of a QFP, but QFNs are usually smaller, so it may be a custom made part library with some errors in measurement.

It's surprisingly easy to do that; especially if the person making the library part isn't the same person that's using it. Maybe the person drawing the footprint only had part of the dimension information for the QFN. I can easily see how someone could take the outside dimensions of the part and the pitch and then come up with something like this based of years of making QFP footprints.

The lesson is to always double check the component fit before sending a board out for fab. In this case, the lead pads are so long that they would short every connection to the ground pad in the middle. Oh, and there's also that giant open via in the middle of the center pad. That's not a good thing.

Duane Benson
Analysis, Mr Schlock?

A Couple of Interestingly Tiny Parts

Yeah, I'm kind of a broken record on this subject. But, you have to expect that given where I work and that I believe in what I do, I'm going to be such a broken record.

I ran across these two parts a while back while selecting components for a robot project 7mmx7mm_qfn_pic of mine. I had 4mmx4mm_qfn_maxbeen using 300mil wide DIP parts and some SOIC packages, but even though this isn't for a commercial venture, I wanted to reduce cost and size a bit.

In the high-volume professional world, this is standard operating procedure but it's also spilling down to the hobby market and the professional prototyping world. Each designer, professional or otherwise, that forgoes a big thru-hole part for something tiny like this, give part makers less incentive to ever build those big packages.

Duane Benson
Lead puppies aren't much fun

A Little Pad In That Via

Here's an interesting via-in-pad situation we ran across a while ago. I'm not sure what the chip is. Probably a processor or an FPGA that generates a bit of heat.

The intention with the layout was on the right track. However, the implementation wasn't really workable. All of those big vias were put there to sink heat away from the thermal pad on the bottom of the chip. The vias being so large, heat would be removed by air convection as well as conduction through the via walls. The thought is good.


In practice though, there are a couple of big problems with this approach. First, the pad on the PCB is much larger than the pad on the chip and the extra area is not masked. Even without the vias, that could make for more difficult solder control. The biggest problem is simply the large open vias. It really isn't possible to solder such a layout with standard surface mount process. Since this is a prototype, we found a way to make it work, but for volume manufacturing, as well as for cost reduction in the prototype, a different approach is needed.


In the second image here, we've simulated what a good workable footprint could look like. This isn't the only possible way to do it, but it would work well. Here, the exposed pad matches the size of the heat slug on the chip. The rest of the pad is still there for thermal conduction but it is masked off. There are a generous number of thermal vias in the masked area and a few capped vias in the solder area. Even better would be to plug and copper-plate over the vias in the solder area, but this way works too and is less expensive at the board fab house.

Duane Benson
Flying spaghetti monster says what?

CAD Library or Substitution Issues

We recently ran across an issue out on the shop floor that was most likely due to the components library inQfn_on_qfp_land  the CAD package. A QFN part was sent for this assembly but the land pattern on the board was just a bit too big. The QFN pads would not reach the pcb solder pads.

Most likely, the designer accidentally selected the library part for a QFP variant of the chip instead of for a QFN. The parts are pretty similar in size if you exclude the leads on the QFP package. It's also possible that someone accidentally purchased the QFN variant when a QFP was called for.

Just one more thing to add to your design-check.

Duane Benson
It's just over that next hill...

Silver via problems

Here's an interesting via situation that I hadn't heard about until just recently.Silver_qfn_vias_v

In these two cases, the engineer has a QFN with a center pad that is required more for grounding then for cooling. Given the lack of criticality, it would seen that the part would give a lot more layout flexibility.

In the photos you can see the area to be soldered clearly. Surrounding that, there are fill areas, traces and vias, all masked off. Look closely at the vias though and you'll see that they aren't completely masked off. There is exposed metal on all of the vias. This creates a risk of shorts to the center ground pad. It may work, but if the QFN doesn't lay perfectly level with an air gap, its center pad can short to these vias. The fact that the intended solder points have vias in them means that it is likely that the QFN will be sucked down flush to the board.

Silver_qfn_vias_hWhat happened here? The engineer intended for the vias to be masked?

Well, it turns out that silver, the board finish in this case, can have problems with fully sealed vias. The silver surface can outgass a bit into the void and cause corrosion. The board house does not cap vias on silver boards to prevent that and without perfect registration, areas of the annular ring end up exposed, as in this case.

According to the board house, gold and HASL surfaces do not exhibit the same problem. We discussed a couple of possible solutions, but in the end, the engineer had the board remade with an ENIG finish with completely capped vias.

Duane Benson

Microvias, Blind and Buried Vias

In a few previous posts, here, here and here, for starters, I've discussed the dreaded via in pad and hopefully, given some useful information about what to do if you must put vias in pads.

In the image, (A) shows an open via which we don't recommend at all. If you must do this, give us a call first to see if we can help you out. We have built boards like this, but we can't guarantee the work when we do and there are things you can do to make it better or worse.


(B) shows one of our favorite options; the copper capped via, also called a blind via by some. You can have the via hole filled with a variety of materials at the boards house for mechanical durability. If this is done properly, we can't even tell that a via exists.

(C) shows a micro via. This usually works pretty good, but you should still call us first to talk about it. Sometimes the solder paste or the BGA solder ball can flow down into the microvia leaving insufficient solder to make a good mechanical or electrical connection. Call us first.

(D) shows the buried and blind via. In this case, the via is completely isolated from the BGA pad so, as with (B), we don't really care.

Duane Benson
Bury that viaspec, Bury that viaspec , bury it, bury it, bury it

Soldermask Via Caps

Today, I'll start with the basics: Soldermask via caps. This isn't the best, but it is the easiest. Almost any board house can pull this one off with a reasonable chance of success. In this example, what we're looking at may be the center pad for a QFN, the metal tab on a D2Pak or a similar smt component with a wide copper area the requires via for thermal relief or grounding.

Soldermasked_vias_for_blog In example A, the via is capped on top with soldermask. Most manufacturers recommend that the soldermask cap diameter be 100 - 125 um wider than the via to minimize voiding and thermal insulation. Interference with heat transfer is minimal in this example.

In example B, the via is capped with a wide soldermask circle. This is a decent method for non-critical applications with larger QFNs. It is easier to do at the board house and should be adequate in most cases other than extremes of signal or thermal sensitivity. It will insulate a bit so you won't get the maximum heat sinking. With this technique, the solder paste stencil must be segmented so that solder paste Will not be deposited on the soldermasked areas.


Example C shows what you should not do - leave the via completely open. Capillary action will likely cause most of your solder to end up on the bottom of your board and not securing your chip. With very small diameter vias, lead-free paste and careful stencil design you may be able to successfully use this design. If you absolutely need to do this, call and talk to our engineers first.

Example D is the least preferable (after C) method. Capping the bottom side will usually keep the solder from dripping out onto the bottom of the PCB, but several other problems can occur. Outgassing from the solder paste can cause the cap to pop off, leaving you with an open via. Solder, especially leaded, can still drain down into the via. You can end up with too much voiding under a QFN or the ball can be sucked off of a BGA. This can work, but, as with C, call us first and talk to an engineer.

Stay tuned. More to come.

Duane Benson

Via in pad methods

Here is another method for dealing with QFN heat slugs with thermal vias. While the best option is to plug the via holes with metal early in the board fab process and then plate over with copper, there are a number of alternatives. We've discussed several of them in previous posts.

Qfn_w_soldermasked_vias Here we have another option. This is for a 9mm X 9mm QFN on a board using an ENIG (Electroless Nickle Immersion Gold) finish. The larger size of this part gives a little more flexibility than some of the real small parts. In this case, while the vias are left open, the area around the vias is masked to keep solder away.

This method can work well on larger QFN and QFP parts, but it is absolutely critical that your solder paste stencil be segmented and not put any solder over the masked parts. (see this post). If the stencil is left fully open or deposits solder paste over the vias, that solder may go down and mess up the bottom side of the board. With a well designed stencil, this may be an easy and reliable method for dealing with your thermal vias.

Duane Benson