Screaming Circuits: QFN and DFN


Large Via In Pad

Large QFN vias I haven't written about via in pad in a while, but the issue hasn't quite gone away yet. This particular QFN, to the left, has the vias tented, which is good. However, it could be better. If you look close, you'll see that they're tented on the bottom of the board with solder mask.

Tenting on the bottom will usually prevent solder spillage out on the back side of the PCB, but with vias this large, the solder will probably flow down into the space, leaving quite a bit of voiding under the part. Sometimes outgassing will pop open the little tents too causing the spillage. And with immersion silver boards, outgassing can cause corrosion in the vias if you have the bottom tented and the top also sealed - like by the part.

If it's a low speed, low temperature QFN that just needs a little ground connection to the center pad, that voiding might not matter. But, in most cases with QFNs, you need minimal voiding for thermal or noise reasons.

The best option for manufactureability is always to have the vias filled and plated over at the board house, but that can be expensive. If you are going to tent with solder mask, this next image illustrates the three Soldermasked vias for blog b ways to do it.

A is the best: a cap on the component side about 100 to 125 microns bigger than the via. B, a larger cap on the component side, or C, a cap on the bottom, will also work but both come with a greater risk of excessive voiding.

Duane Benson
Do solder mask tents need a rain fly?
In Oregon - probably yes.

Many Faces of the QFN

When I first started using a CAD package for circuit design, I couldn't understand why the software didn't come with all of the standard footprints and why that wouldn't be good enough. That level of ignorance was hopefully pretty short-lived. But back then, things were a bit simpler. Most of what I dealt with were in DIP packages - 0.1" lead to lead spacing and 0.3" or 0.6" width.

QFN copper layer QFN solder mask layer Even if the reality was never that simple, it's a lot more complex now. Take the simple QFN. Your CAD package probably has a decent variety of QFN footprints, but most of them probably look like these first two here.

On the left is the generic footprint with a wide open flag pad in the middle. On the right, the cross-hatched area is likely representative of what the solder paste layer looks like for that standard library part. Looks simple, but there's a whole lot more to the QFN (and DFN).

Take these next two images. The image on the left here shows what should be a pretty common standard solder paste layer for a QFN center pad. You want to keep the paste coverage down in the 50 - 74% range QFN solder paste stencil layer good QFN Freescale eagle copper layer to prevent the QFN from floating up during reflow.

Some QFNs, especially high-frequency and RF parts require a special copper pattern to ensure proper grounding and clean signal conditions. This one on the right shows the recommended copper pattern for a particular Freescale ZigBee radio chip.

Even if your CAD package seems to have the QFN covered, check the component data sheet for any special land pattern requirements and check the paste layer to make sure it has you covered to prevent float or voids.

Duane Benson
One face, two face
Red face, blue face

Inverted QFN Land Pattern

Have you ever experienced the heartbreak of inverted land pattern? It's not supposed to happen, but every now Inverted QFN land pattern 2and then, it does. Maybe something happened when creating a custom footprint. Maybe, somehow it got inverted in the CAD software and then placed on the wrong surface layer.

Maybe it was a subliminal attempt to make up for those giant open vias in the thermal pad. Who knows. But, it happened, so now what?

You could re-spin the whole board. Ugh. That's, like, wasteful and stuff. Certainly, if this is a production build, you'll have to re-spin. For some prototype applications - like if it's a high frequency or RF thingy, you may very well have to get a new set of PCBs fabbed up too.Inverted QFN land pattern

But, sometimes in the prototype world, you may be able to salvage the board run. We used to do stuff like this all the time with  thru-hole parts - need an extra chip, just dead bug hang it on up there. 

Flip the chip over and use some small gauge wire - maybe wire-wrap wire - and hand wire to the upside down chip. Gluing it down first may be helpful. Just keep in mind that since the thermal pad isn't soldered to the board, you will lose some of your thermal performance. Maybe solder a small heat sink on it or something. And don't forget to wire that pad to ground too (if it's supposed to be grounded).

Duane Benson
Just put it on the seventh surface of your tesseract and it will fit right.

What's Wrong With This Picture?

Vias through stencilopeningsWhat's wrong with this picture?

I forgot to warn you that there'd be a pop-quiz. It's only worth 10% of your final grade though, so not to worry.

We're fully into the rainy season here in Oregon now. It's dumping and the puddles are puddling up. Last weekend, we thought we were in for another big snow and ice mess, like December 2008, but it turned out to be just media hype. We warmed up and it's back to the usual 40 degrees and raining.

Unlike with a QFN thermal pad, we do want open holes in our streets. We want the liquidy stuff to go down underneath and not stay up top, 'cause that would make our feet wet and Johhny doesn't like wet feet.

Duane Benson
If it's bipolar, it's a "collector." If it's a MOSFET, it's a "drain." What is it if it's a street?

Tented QFN/QFP Via in pad

Tented vias in padHere's a pretty decent example of mask-tented vias in the thermal pad of a QFP. Most manufacturers recommend no more then 100 - 125 um wider than the via to minimize voiding and thermal insulation in cases like this. This is a reasonably inexpensive way to handle vias in the thermal pad. Sometimes though, the tents will pop open allowing solder to wick down through the via.

The mask over the center via on the right looks a little thin, so you'd want to give it an extra look over after reflow to make sure it's okay. (We'd do that here, of course)

We'd rather not see this technique on really small parts because it gets difficult for the fab house to put the mask down with enough precision. With small parts, filling and plating over the vias is the preferred technique. Well, that's always the preferred method. It's just more important with smaller parts and BGAs. This method is acceptable for most QFPs and larger QFNs though.

Duane Benson
All your via are belong to us

QFN Solder Mask Issues

Here's another QFN oopsie. Presumably, in this case, the flag pad on the QFN is needed as a heat sink and those vias are designed to conduct heat to the other side of the board. That's all good. But, with the solder mask covering everything but the vias, it won't work. I'm guessing this was an accident.

QFN-reverse-mask The stencil looks okay. It's segmented to reduce the amount of paste. We here at Screaming Circuits recommend 50 - 75% paste stencil coverage, as do most QFN component manufacturers. But, again, on this board, it will all go to the wrong place. It will wick down the vias to the other side and may not connect the pad to the part at all.

The best option would be to have the vias filled with a thermally conductive material and plated over. Most fab houses can do this as a matter of course these days. The second option, would be to use slightly smaller via holes and reverse the mask so solder mask is capping the via holes and the rest of the pad is exposed for soldering.

Duane Benson
And keep moles out of your via holes too

Lets Get Small

I’ve been slowly working on this microcontroller board (very slowly) for a while. I’m using PCB123 and some new, very small components to put it together. I’m amazed at the changes that have happened recently in this industry. Change has been a constant in this industry since it’s been around, but it only seems to be accelerating. Or at least, it’s taken a big jump just recently.

DFN-8 I’ve made size an important constraint so I picked a low drop out MCP1726 regulator instead of the venerable LM7805 or equivalent. In the old days, if size was a concern, I’d skip the TO-220 package and instead use something in a TO-92 package. But that would limit me to around 150ma, and it's a thru-hole part. That’s fine if it’s only the microcontroller, but I want to drive a bunch of LEDs, and I2C bus and some other logic circuits.

The old TO-220 package was about 10mm X 20mm plus the area needed for a heat sink to deliver a full amp. What amazes me is that this new part comes in an 8-lead DFN (same thing as a QFN –Quad Flatpack No leads - but with leads on two sides instead of four). It’s 3mm X 3mm and, with proper PCB design, can supply the same 1-Amp that the TO-220 packaged part could deliver with something like 50 times the surface area, not even including the heat sink.

Duane Benson
The parts, they are a shrinking.

Speaking of Common QFN Issues...

Classic via in qfn pad Here is the classic QFN via in pad. It simply isn't possible to solder the center pad properly with that much open via real estate.

The best way to deal with this is to fill the holes with something that will still do a good job of conducting heat away and then plate over the holes.

Barring that, you could put solder mask caps over the holes on the component side shown here. Most manufacturers recommend that the soldermask cap diameter be 100 - 125 um wider than the via to minimize voiding and thermal insulation.

Some people will put soldermask caps on the back side of the board. That may work, but it still tends to be problematic. Solder can still wick down in the vias leading to excess voiding. The via caps can pop open resulting in an open via that sucks solder off of the pad.

Duane Benson
Look closely and you might see Paul Lynde in the center via

Novel QFN Land Pattern

Novel QFN groundingBecause the center land is so much bigger then the side pads, QFN solder paste can be a problem if not handled properly. I've written about options before, but here's another approach. I ran across this QFN land pattern the other day.

This one's a bit easier to start with because either there aren't any vias needed or they and filled and plated over. It also looks like there isn't much of a thermal issue here. In some cases the center pad is needed for heat sinking, but in other it's just there as a ground. My guess is the latter is the case here.

By creating a bunch of openings that are the same size as the side contacts, this QFN will get good grounding and there won't be any issues with too much or too little solder paste getting in the way. It pretty much bypasses the standard QFN problem.

Note that the designer must have the same pattern in the solder mask layer as in the paste layer. If only the paste layer was like this, the solder would spread out and there would likely be too much voiding. It might not connect in the center at all. If only the mask layer was like this and the paste layer was fully open, there would be so much solder with nothing to stick too. It would just be a big mess. Yuck ☠.

Duane Benson
QFN Tetris anyone?

PCB123 QFN 28 footprint

First things first. I still haven't received the little ZigBee modules. Microchip said they'd ship out on the 14th so I shouldn't expect any different. I'm going ahead and getting started on the schematic anyway.

When I get the modules, I'll probably write the code and try them out on an old PIC board that I designed and built a while back. But eventually, I want a nice small integrated package so that means a new schematic and layout. I have the schematic partially done in another CAD package, but I'm rolling with Sunstone's PCB123 this time.

QFN28 footprint drawing The first thing to do is start looking at the components. I expect the footprints will be there for all of the passives, but given that PCB123 V3 is fairly new, I would also expect that some of the more complex parts won't be there. I'm tackling the PIC 18F2321 in a QFN28 package first. It will be a good opportunity to see if I can follow my own advice and make an easily and reliably manufacturable library component.

Most of it will be easy, but I will likely put some vias in the center pad area. I'll mask them properly. I'll also make sure that I create a proper paste stencil area. It's a 6x6x0.9 mm, 28 lead QFN package. The datasheet has the basic outline, but it also references a more detailed packaging specification on the Microchip website. I'll go there and get as much footprint information as they have.

Of course, even there I can find room for confusion. Microchip lists eight 28-Lead QFN footprints. Ugh. Just to be clear, this is the 6x6x0.9 mm with .40 mm contact length. Page 135. Ironically, the page in that detailed specification is the same one as in the datasheet and it even uses the same "For the most current package drawings..." statement referring to it's self. And no where in this 192 page document could I find anything on the paste layer. I'll segment the paste opening in the middle pad and shoot for about 50% coverage.

Duane Benson
You must go here to be told to go there