Package Variants

Cap under connector footprint Here's another issue we see from time to time involving the old, familiar, 0.1" pitch headers. Break away header When initially laying out the board, the footprint for the break-away header is used. It's small and easy to use. The headers are cheap and easy and you don't need to stock a bunch of different pin-counts.

That's all fine and dandy until the next rev of the prototype when you decide to change to a shrouded header for the additional reliability and pin protection afforded by it. When making that change, don't forget that the footprint with the shroud may very well be bigger than the break-away footprint.

Shrowded header In this particular case, it wouldn't have mattered except for the capacitor that ended up under the shrouded header.

Duane Benson
Get out of my cap's space, man

And The Race Goes On

AUP package The race for the smallest part is still going strong. That and the fact that basic logic gates are still with us is affirmed quite well with a new set of chips from NXP. The 74AUP2G00 is a dual two-input NAND gate in a no lead XSON8 package at just 1 mm x 1.35 mm. That's not the scary part. The scary part is the lead pads under the part are 0.15 mm wide and just 0.35 mm pitch center to center. That's 5.9 mils and 13.8 mils respectively. The gap between the pads is 0.2 mm (7.8 mils).

To put that in a little bit of perspective, an 0201 passive component is 24 mils x 12 mils. An 01005 is 16 mils x 8 mils.

Above right is a land pattern for the part with an 0201 bypass cap next to it. The trace going from the pin to ground (Pin 4) is an 8 mil trace. The trace going to VCC (pin 8) is six mils. The via is a pretty standard 24 mil via. As you can see, an eight mil trace and space isn't going to do for a board with this size of part on it. Six mil is really even a bit too big.

Duane Benson
La de da de de, la de da de da

Picking Packages

A long, long time ago, in a place pretty close to here, picking a form factor was easy. Your CPU came in a 40 pin DIP. Your logic came in 14 or 16 bit dips. You picked resistor sizes based on their current carrying needs. Transistors and other power components got a lttle more difficult, but not much. It was largely a matter of power disipation requirements.

Different story now, though. First, there's thru-hole vs smt. Then there's a plethora of options beyond that. So, what really matters? A specific resistor size may come in multiple wattages. Chips come in multiple packages - often from big DIPs all the way down to tiny QFN or BGA packages. Let's look at a few examples.

Here's a simple microcontroller: the PIC18F25K22. It's a pretty typical 8-bit PIC. You can purchase it in four different packages:

  • DIP, $2.05 each, Qty 100, Tube
  • SSOP, $1.86 each, Qty 100, Tube
  • SSOP, $1.90 each, Qty 2,100, Tape & reel
  • QFN, $1.86 each, Qty 100, Tube
  • SOIC $1.89 each, Qty 1,600, Tube
  • SOIC $1.93 each, Qty 1,600, Tape & reel

(DigiKey prices as of the posting date. Some are non-stock items) There's also the part presentation to consider, e.g. reel, cut tape, tube.

Next, look at a 1K resistor that might be used as a pull-up. (As listed in DigiKey) Thru-hole resistors range from 1/20th Watt up to multiple Watt packages. SMT parts range from 1/32 Watt up to lots. Simplifying a bit and just looking at 1/4 Watt, you can purchase 0402, 0603, 0805 and 1206 packages. For high volumes, price will be a factor, but for lower volumes, the price difference can be trivial.

If you have plenty of space to work with and you need to build by hand or for some reason need a socketed part, your choice is the DIP. If space is a bit of an issue and you may or may not hand build, then an SOIC is probably your pick. Some people will hand build QFNs and SSOP packages, but that's not realistic in anything but rare cases.

When size, speed, current or performance need to be at maximums, selection is still not that difficult. You'll often have far fewer options to choose from at the performance edges. But when there's headroom all over the place, how do you decide? Why an SOIC over n SSOP over an QFN? Why 0603 over 0402, 0805 or 1206?

Duane Benson
Peter Piper picked a peck of pickled PIC packages.

 

Who's Right?

Jack commented on my prior post, An Unanswered Question. His point was that instead of just saying "check with the manufacturer's datasheet", like I so often suggest when talking about land patterns, I should give more credit to the IPC and understand that many datasheets are the result of less than thorough study. That's a very good point.

The challenge is that some manufacturers do a great job of figuring out how to use their packages, such as Ti with their Package on Package (POP) OMAP, or Freescale with some of their ZiBee chips. u-blox has done a good job of documenting paste mask requirement for their castelated mounting configuration too. On the other hand, some other manufactures seem to have just cut and past part of an old data sheet without even giving it a once-over. As Jack mentioned, with some of the newer packages, IPC doesn't always have the data yet. I didn't see that IPC-7351B covers 0.4mm pitch BGAs yet. It does do a good job of covering the need to segment the solder pastes stencil over a QFN center pad, which I also have written about here more than a few times.

I guess my thinking is that the part manufacturer should be the best equipped to tell us how to use their components. To Jack's point though, that would be in an ideal world. But, reality rarely holds up to the ideal. Some manufacturers do quite well and some seem to virtually forget that they even made the part once it's out of the development labs. IPC does a very good job but isn't necessarily the most current. Then, of course, some manufacturers don't follow the IPC guidelines. Board fab houses and stencil makers have a lot of good data too, but also aren't always up to date (nor are assembly houses).

I suspect that I get a little cynical on this subject in general because we see so many diversions from standard come through our shop. The designers, by and large, would much prefer to lay out their boards for greatest manufacturing success, but so many of them have a very difficult time finding the necessary data.

In some ways, I think the environment is getting better. More people seem to be aware of the need for good standards and to follow those standards. IPC seems to be pretty quick in adding in newer packages. The IPC land pattern generator is a big help. But the proliferation of new parts in new form-factors negates a lot of that gain.

Duane Benson
I'm not convinced that in net, this post has any actual content.

Hot Time in the Small Chips Tonight

Years ago when I worked for a local projector company, we were introducing a relatively compact projector lighted by a Halogen lamp. Cooling such bulb in a big, wide open projector wasn't a problem, but we barely had a few cubic inches of open space around the 400 Watt "heating element" in our projector. Our engineers had to dig up old and nearly lost information about cooling high-powered vacuum tubes in constrained places.

We don't have to worry about cooling glass devices, and big processors, big regulators and other big power components have needed heatsinks and fans for quite a while, so cooling isn't really a new science. But the science of cooling is changing. We're seeing more and more tiny components needing advanced power dissipation techniques.

With our projector bulbs, just sticking a fan next to the bulb wasn't good enough. These new tiny power components, like the MCP1726 regulator, have a similar issue. You can't just stick a heat sink on them and call it good. You need to engineer the cooling system with thermal planes, thermal vias and other layout considerations. Some, like the CMLDM7484, a dual MOSFET from Central Semiconductor, in a 1.7mm x 1.7mm package, ask for aluminum or ceramic core PCBs to survive its maximum power dissipation. Using the PCB for cooling can be a lot more complex than cooling with heatsinks and fans. Anyone remember how to cool a vacuum tube base area and PCB surrounding it?

Duane Benson
Kelvons have feet, but photons can fly.

BGA Woes

Quite a few of the new chips I see coming out stick to the BGA or QFN form-factor. Sometimes they'll be referred to as WSP (wafer scale package) or CSP (chip scale package), but those are still just little BGAs. Some do show up in larger packages, but many of the really new designs seem to stick to these form-factors.

A few years back, we tended to see a lot of design problems related to regular, big BGAs (0.8mm or greater pitch). Things like black padmicrovoids and via in pad cropped up to cause proto-headaches. While those problems still show up from time to time, they have become much less frequent. No, we're seeing issues with the tiny ones - 0.5mm and 0.4mm BGAs, CSPs and WSPs.

With a big BGA, you can route to vias in between the pads. That's easy. With the small ones, especially 0.4mm, you can't. You have to put the vias in the pads. Of course, you have to fill and plate over the vias. Big BGAs tend to prefer non-soldermask defined pads (NSMD) while some of the 0.4mm BGAs require soldermask-defined (SMD) pads. A really flat surface is more important for the tiny parts too. Don't fear extra small parts, but you may need to do a bit more homework and relearn a few old rules-of-thumb.

Duane Benson
I'm solderin, I'm solderin, I'm solderin for you

A Bit More On the LGA

After my last post about LGA land patterns, I received a couple of questions asking for more detail in a few areas.

"The LinearTech  LGA apnote (LTM46xx series) shows planes on the mounting layer interconnecting pads that are solder mask defined. This is supposed to be for heat dissipation. Will smaller copper defined pads and vias to full internal copper ground and power planes provide adequate cooling?

What about using LGAs on the same layer as BGAs? BGAs have copper defined pads? We've been sending 1:1 soldermask gerbers to the fab house so they can adjust per their process. Can this be done selectively so the SMD LGA pads don't grow bigger? What kind of Fab Note should be in the "Readme" file?

Also, please warn LGA users to be careful using wizards (eg Pads Layout) to generate the pad numbering. Linear Tech's LGA does NOT follow the standard BGA alpha numeric numbering. I don't know about other LGA mfgrs numbering systems but ... Double check the pad numbering and avoid this nasty snake bite!"

First, as far as cooling goes, the answer, unfortunately is "it depends on how closely to the limits you are driving to part." You will get best results with more surface copper. That being said, you can use vias to internal and back-side planes to increase heat dissipation. Ideally, you would have Lot's of surface copper and vias to the internal and back side planes, but that's not always possible. The vias that are not under the LGA pads can be left open. Any vias in an area to be soldered must not be left open. Ideally, you would have them filled with a thermally conductive material and plated over. You do have some flexibility to reduce the surface copper and replace it with vias to other planes, but ultimately, the final answer will only come from your design testing.

You can have NSMD and SMD pads on the same PCB. How to do it is the big question here. Many fab shops will make their own decision on what is "best" for your PCB in this regard. I would speak with the board house and get their recommendations on how best to specify what you need in terms of NSMD and SMD mixed. You'll probably have to follow a slightly different procedure for each different fab shop.

I would double echo the comment about using caution when using wizards to create a land pattern. Not all manufacturers follow the same numbering scheme. You could get bitten badly with this one.

Duane Benson
Who was that soldermask defined man?

Et Tu Embedded Passives

I don't know if or when embedded passives will become the "next big thing" in PCB design, but they are on the way. We, at Screaming Circuits, have been asked about the use of embedded passives a few times.

Embedded passives
The purported advantages of the technology lie primarily in the ares of cost reduction and space reduction. You could potentially get your bypass caps much closer to where they need to be as well. The space parameter is pretty obviously an advantage, but the jury is still out on costs. I suspect that at this moment, it's pretty difficult to find a board house that can fabricate a PCB with embedded passives.

If you're not familiar with the concept, capacitors or resistors are built up on the inner copper layers of the substrate. There are a couple different methods used such as plating, printing or thin-film. As shown in the illustration, the resistors and capacitors inside the PCB negate the need to mount them on the outside. I can see rework being a problem if any of those embedded parts has issues.

In terms of assembly, we wouldn't treat such a board any different than any other PCB. If your fab house notes that there are temperature or any other restrictions, let your assembly house know. Beyond that, all the standard rules apply.

Duane Benson
Note from Forbin: Colossus is watching

Land Patterns - Equal and Not Equal

I was recently asked a question about QFN package varieties. The questioner wanted to know if different package variants of 16 contact QFN packages, such as HUQFN, DHVQFN, SQFN and such, all shared the same footprint.

If they did, the CAD work would be much easier. There would be one land pattern to worry about and that would be that. Unfortunately, that is not that and in this case, that, in fact, that may never be that.

Many different varieties of QFN packages could use the same land pattern, but they don't always do. Some will have the same pitch, but more distance between the outside contacts and the corner, thus a greater overall dimension. That can happen even with the same labeled variety of QFN package. Some will have different dimensions, differnt pitch, different pad sizes or different thermal pad sizes. Sorry. No easy answer here.

I popped on over to the NXP website, one of our Circuit Design ECOsystem partners, for some examples. NXP lists two 60 contact HUQFN part packages. One is 5mm x 5mm. The other is 6mm x 4mm. Same with the HVQFN. There is a .65mm pitch 4mm x 4mm package and two.5mm pitch 3mm x 3mm parts with a different overall package outline.

In general, generalzations aren't going to work here. You're going to have to go dig out that datasheet and quite possibly create a new land pattern.

Duane Benson
One pattern to rule them all and in the solder bind them

Window Pane in not a Pain

QFN parts (also known as MLF or Micro Lead Frame) parts used to cause a lot of problems a few years ago, as evidenced by the number of blog posts covering the subject.

Can I use my own blog as cited evidence to justify my own conclusion? Doing so is probably bad form, but I'm doing it anyway. Interestingly, if you look up "citations" in Wikipedia, the entry (as of this writing) has a note indicating that the article on citations has insufficient in-line citations. Hmmm.

Screaming_QFN_Fig1 Anyway, it seems that the industry in catching up with the proper manufacturing methodology for use of the technology. It's important enough though that it bears repeating now and then. The key to successful QFN and DFN manufacturing really is in the solder paste stencil pattern. Consult the data sheet for the part, but if you can't find the datasheet or if it doesn't cover the stencil layer, use the window pane technique, or "segmenting" for the stencil layer when you're making the library part for your CAD software.

If you leGood QFN stencil bave the full thermal pad area fully open, you'll most likely end up with too much solder in that area. The part will ride higher than it should and may very well float too high for all of the pads on the  side to connect. See the top  part on the above right illustration.

Shoot for 50 - 75% paste coverage by segmenting the stencil as in this illustration on the left here. That'll ensure that the center pad and the side signal lands will be at the same level. You'll get much better yields and reliability.

Duane Benson
The strangest sight I've ever seen
2 buffalos, 2 buffalos, buffalos on my lawn.