Land Patterns - Equal and Not Equal

I was recently asked a question about QFN package varieties. The questioner wanted to know if different package variants of 16 contact QFN packages, such as HUQFN, DHVQFN, SQFN and such, all shared the same footprint.

If they did, the CAD work would be much easier. There would be one land pattern to worry about and that would be that. Unfortunately, that is not that and in this case, that, in fact, that may never be that.

Many different varieties of QFN packages could use the same land pattern, but they don't always do. Some will have the same pitch, but more distance between the outside contacts and the corner, thus a greater overall dimension. That can happen even with the same labeled variety of QFN package. Some will have different dimensions, differnt pitch, different pad sizes or different thermal pad sizes. Sorry. No easy answer here.

I popped on over to the NXP website, one of our Circuit Design ECOsystem partners, for some examples. NXP lists two 60 contact HUQFN part packages. One is 5mm x 5mm. The other is 6mm x 4mm. Same with the HVQFN. There is a .65mm pitch 4mm x 4mm package and two.5mm pitch 3mm x 3mm parts with a different overall package outline.

In general, generalzations aren't going to work here. You're going to have to go dig out that datasheet and quite possibly create a new land pattern.

Duane Benson
One pattern to rule them all and in the solder bind them

Need a Reference for the Reference

Not long ago, I wrote a short post about non-standard use of reference designators. After doing that, I've been looking at some of my own microcontroller and motor driver boards with an eye for how close to standards I am.

All of the R's, C's, D's and U's are okay, but there are some differences. For example, the Eagle library I've been using calls crystals "X" instead of the more standard "Y." I have seen crystals designated as "X", "Y" and "Q." LEDs seem to go by "LED" instead of "D" as indicated in the Wikipedia list. Headers go by "J", "JP", or "H." Wikipedia says "J" is for a female jack connector, "JP" is for jumper, and it doesn't list a "H." My board has break away two-row male headers and keyed single-row male headers. Wikipedia does note that its list is a set of commonly used designators. Not necessarily standard.

We probably do have the specific standards document laying around here someplace, and if I were doing real work on a professional basis, I'd hunt it down and make sure I followed the actual standards. But I'm not doing real work with my controllers and drivers, so I just do the best I can. I wonder how often that happens everywhere. The standards books are "somewhere" but no one really knows where.

Duane Benson
Somwhere over the reflow...

AT Tiny is Tiny

I just spotted a note on Twitter, from SiliconFarmer, referring to the ATtiny44A coming in a 0.45 mm pitch QFN as well as a 0.5mm pitch MLF package. (In practice, an MLF is the same as a QFN, by the way.) Just in case you actually care, we're on twitter at "pcbassembly".

I've run across a number of 0.4mm BGA packaged parts, but this is the first sub-0.5mm QFN I've seen. Interesting that they have two different sizes of QFN package, one at 4mm x 4mm and the other at 3mm x 3mm. If you're that tight on space, that little 7 square mm of extra open area can make a difference.

Screaming Circuits won't care on the assembly floor. We do plenty of 0.4mm parts so a 0.45 isn't anything new. The most important thing to remember is to use the right footprint. It's easy enough to accidentally use a QFP footprint when you have a QFN (like here). I could see it being even easier to swap for the wrong footprint with this part. Doing so would be bad, most certainly. You might get one or two contacts per side on the right footprint, but that's pretty much as good as none.

Duane Benson
It's like Ice-9. The same, only different.

Little Chippy Challenges

And in terms of "Chippy", in this context, I'm referring to chip-caps and any other tiny little two-connector components. When considering surface mount, most people think of the many-connector parts, like BGAs and QFNs as the challenging components. That's mostly true. However, the little passives can be big bears too if not treated properly.

You can have tombstoning problems. This can be caused by unequal sized pads, unequal sized traces going to the pads or inequality in copper plane in a different layer. A big part on one side can cause tombstoning too - the big part's thermal mass may slow the solder paste melt on one side of the part, leading to  tombstoning.

Via-in-pad is still a problem too. Open vias can lead to unreliable connections, tombstoning or crooked  parts.

Solder mask can cause problems too. Too thick a solder mask can prevent the part from reaching the solder and can cause tombstoning. That thick solder mask can also interfere with out-gassing in the reflow oven which can cause solder ball splatter. (A = okay, B = at risk if mask is too thick).

Duane Benson
It just goes to show you...
It's always something.

Scoopage

I wrote recently about segmenting your solder paste stencils for the big open areas on your QFNs. The idea is that if the entire area is left open, it may end up with too much solder in the heat slug area, causing the part to lift up and not solder properly.

CadstarGuy commented: "Also - when you have the full aperture in the stencil it can tend to drag as it is pasted leaving big gaps in the solder (and excess solder on the screen)." 

That's a very important point to remember. Ironically, leaving the area fully open can lead to either too much solder or not enough solder. Weird. Huh? The solution is the same: segment your stencil layer inside that center pad area.

Duane Benson
Anoid the void!

Missed it by That Much...

Running a DRC (design rule check) before sending your PCB out for fab and assembly is a must. It's also a minimum. Not everything is caught by all DRCs.

For example, if you look at these PCB images, you'll undoubtedly spot the problem right away. These passed the Eagle DRC. I'm not saying all CAD packages will miss this kind of thing, but you should always expect that something might get through.

Of course, if you end up selecting the wrong component footprint, or if the footprint library part was created incorrectly, the DRC definitely won't catch it. A DRC also won't likely help if you output your Gerbers incorrectly, i.e., positive output vs. negative output.

Just like you don't completely trust an autorouter, you shouldn't completely trust your CAD packages ERC and DRCs. Spend a little time manually double checking things too.

Duane Benson
Bring out the cone of silence

Pad is as Pad Does

I've recently written a bit about soldermask and pads relative to BGAs. In most cases, we recommend NSMD (Non Solder Mask Defined), or copper pad defined, pad for BGAs. With the BGAs, the NSMD pads will allow the BGA to sag down just a bit more and adhere to both the top and the sides of the pad, resulting in a better mechanical connection. The exception seems to be 0.4mm pitch BGAs with a straight matrix alignment as in the illustration the link above. Ti, with their Beagleboard project found that NSMD pads tended to lead to bridging and had much better results with SMD pads. Staggered BGA lands should still use NSMD pads though.

Along with the 0.4mm BGAs, not all parts need or want NSMD pads. International Rectifier has a package called "DirectFET" which is designed to use solder-mask-defined layouts. In this package, the FET source and gate connections are directly on the FET die. The drain connection is a plated copper can directly bonded to the drain side of the silicon die. This system gives a very low-loss capable part with great thermal conduction properties.

Internal Rectifier recommends solder-mask-defined pad layouts. Take a look at their application note 1035 for complete details on designing with this package. I might try the form-factor out myself some time. It always bugs me that a 100 Amp MOSFET might only, in practice, be able to pass a small chunk of that amount of current because the leads or internal interconnects would otherwise melt. The DirectFET package should aleviatemuch of the melting problem.

Duane Benson
Melting is good if you're talking about toasted cheese

Window Pane in not a Pain

QFN parts (also known as MLF or Micro Lead Frame) parts used to cause a lot of problems a few years ago, as evidenced by the number of blog posts covering the subject.

Can I use my own blog as cited evidence to justify my own conclusion? Doing so is probably bad form, but I'm doing it anyway. Interestingly, if you look up "citations" in Wikipedia, the entry (as of this writing) has a note indicating that the article on citations has insufficient in-line citations. Hmmm.

Anyway, it seems that the industry in catching up with the proper manufacturing methodology for use of the technology. It's important enough though that it bears repeating now and then. The key to successful QFN and DFN manufacturing really is in the solder paste stencil pattern. Consult the data sheet for the part, but if you can't find the datasheet or if it doesn't cover the stencil layer, use the window pane technique, or "segmenting" for the stencil layer when you're making the library part for your CAD software.

If you leave the full thermal pad area fully open, you'll most likely end up with too much solder in that area. The part will ride higher than it should and may very well float too high for all of the pads on the  side to connect. See the top  part on the above right illustration.

Shoot for 50 - 75% paste coverage by segmenting the stencil as in this illustration on the left here. That'll ensure that the center pad and the side signal lands will be at the same level. You'll get much better yields and reliability.

Duane Benson
The strangest sight I've ever seen
2 buffalos, 2 buffalos, buffalos on my lawn.

Mismasked PCB

Personally, I think this PCB and stencil is prettier with the green showing through. It breaks up all of the boring silver color. It adds some life in.

...unless you are a chip wanting to be soldered down. If that's the case, then it doesn't look so attractive.

Whomever really, truly and universally solves the library problem should get a Nobel prize or a Pulitzer. Maybe a free latte. Something tells me the problem won't be solved in my lifetime though.

It really shouldn't be that difficult. How many different package form-factors are there? Yes, a lot, but a manageble lot. The problem comes in when you have to match those footprints to the millions of schematic symbols. Maybe there could be a way to decouple the specific footprint from the schematic symbol.

The schematic could have its pins defined to an abstraction layer and then that abstraction layer could be automatically connected by the layout CAD software pin to pin on the specific footprint selected. Maybe. We can dream, can't we?

Duane Benson
I'm happy I live in a split-level head

Funky QFN Land Patterns

I've described the optimal way to create your land and solder paste layer for QFNs a couple of times before. But that was for a standard square QFN or rectangular DFN. What happens if you look at the bottom of your QFN and it's all weird like this one?

Does it require a different philosophy for the big pad areas? Should it just be a solid opening because their is more than one thermal pad and they don't cover the whole area?

Well, this pic is an Intersil ISL8200 power module. It's pretty cool and Intersil was kind enough to actually put the paste layer recommendations right in the data sheet. Unfortunately, not all chip manufactures do that.

The bad news is that it's a pretty complex pattern. The good news is that the data sheet gives a diagram with great detail on the required dimensions for the lands and the stencil. And, yes, you treat this just like any other QFN thermal pad. They recommend 50 - 80% paste coverage for the thermal pads just like everyone else. That means that you'll segment the paste cut-outs in the paste layer for each of the four thermal areas just like you would for the whole pad area on a standard QFN. The data sheet for this part has the specifics.

For similar parts from other manufacturers, you should go to their datasheets and app notes first, but if you don't find a recommendation, we would suggest you do the segmenting and shoot for somewhere between 50 and 80% coverage. Putting down too much paste is a bad idea for any QFN or DFN, but it's probably even more critical with a part like this where the solder areas only cover half the part. If there's too much solder on the underside, it will likely tilt and most likely not solder reliably.

Duane Benson
Don't eat paste.