Screaming Circuits: A Question on Schematic Style


A Question on Schematic Style

Just a quick question here...

FPGA and caps schematicI'm placing the components for my TinyFPGA based stepper motor controller board (see the prior articles here first, here next, and here last). Specifically, I'm finding places for all of the capacitors. That's where the question of schematic style comes in.

When I first started using computer based CAD software, sometime shortly before the stegosaurus roamed the land, I would position component symbols on the schematic near the chips they belonged with. Doing so made it easy, come layout time, to remember which capacitors go where.

Since then, though - and I don't remember when I started this - I've started following the practice of grouping capacitors on the schematic, as I've done on this sheet to the right. All of the capacitors are up at the top, shown connected to V+ and ground rails.

That's not a problem when they're all 0.1 uf bypass capacitors and each chip just takes one. However, with higher speed and more complex chips, multiple bypass caps or different values are often required on each chip.

Now, when I go to layout, I need to go find my component data sheets again (they really should never be very far away) and re-figure out what combinations of bypass capacitors go to which pins on what chips.

I like the cleaner schematic that results from grouping bypass caps, but it's adds pain and a bit of opportunity for error during layout.

What style do you use and why? Am I an idiot for doing it this way? Wait. Don't answer that last question.

Duane Benson
Six of one and 12 × 5 × 10-1 of another


@Aylons - That sounds like a good approach as well.

I use a mixed approach. I group capacitors by values for each IC I'll use, and try to keep each near the IC or pins where they'll be required. I may use blanket parameters to annotate which pins they belong to, if this is not clear by inspection - it usually is. Capacitors that must go on one specific pin may be placed alone, directly wired to the pin or placed near it.

I also try to adapt the schematic representation for the IC to make this work better. So, when I'm reading the schematic to generate the schematic symbol, I take this decoupling recomendations intoa account to group the capacitors.

@Matthewtoo - That Ti reference makes a lot of good sense. Everything has a clear home. The doc shows more examples on other pages as well. I don't remember exactly when I started just grouping all caps with no notes, but I think that needs to stop.

(oops, I'm a different Matthew!)

I quite like the decoupling cap schematic style in this TI document: (page 23)

@Gordon - I think I'm going to need to go back to associating caps with the assigned chip schematic symbol. I don't design complex boards, so I can usually get away with putting them in a common area, but give me a few chips with a bit more stringent needs than I'm used to, and my regular system falls down.

@Matthew - I checked out that video. Now that is a slick feature! The effective bypass radius circle would be very useful as well.

One of my less fond memories of being a repair technician in the 70s was poring over giant schematic sheets, looking at long lists of bypass capacitors and grumbling while I tried to figure out which one was supposed to go with which chip. Back then it was more trying to figure out which tantalum cap had shorted out yet again, though you're right that all the ceramics were (mostly) the same value so that part wasn't a big deal. Still, because of that experience I've always snuggled my bypass caps up to the chips they're buddies with when drawing my own schematics. And been glad I did so, more than once. Saved me some cursing energy. ;-)

Check out the 2 minute mark of this video to see how Cadence PCB Editor allows decoupling capacitors to be assigned to an IC so placement of your caps is easy

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