Screaming Circuits: September 2011


ESC Robot Attendees

ESC Boston 2011 016 cr (Medium) We've been hanging out in Boston at the ESC show. Yesterday was a busy day with lot's to look at and lot's of folks at our booth. Some human, some not. The Freescale people, just a few booths down, brought along a tele-presence robot.

The little guy wanderd here and there a bit. It's a cool concept, but I think it didn't quite live up to it's potential. They really should have registered it as an attendee. It did have a little card hanging around it's neck, but I don't see why it couldn't have had a genuine show badge. If it were me, I would have had it actually stopping by booths, talking to people and collecting goodies.

Still, it was a fun demo and, presumably, an example of Freescale chips in action.

Duane Benson
I salute our new robot tradeshow overlords

Small Open Vias

Tiny vias in qfp pad Parts change and so do vias. Our standard policy here is that open vias in pads are bad. We from time to  time recommend ways to plug them. Generally, you have several options. Like this post shows. However, with vias in the pads of really small parts, those solder mask options will probably not work. Solder mask generally isn't put down with enough precision to cover holes on tiny pads, and further, the solder mask would probably mess with the clearance. On the left is an example of a small QFP with open vias in the pads. Those are some small vias.

So, if solder mask isn't going to work, what QFN center void open vias will? Filling and plating over them. That's what will work. You really only have two choices: fill and plate, or live with a bunch of voids under the part and solder slopped on the bottom side of the PCB. Here on the right are two illustrations representing the issue.

In the top half of the image on the right, I'm representing the vias with copper plugs and plated over at the board fab house. As with all parts of this sort, there may still be tiny voids. IPC and the manufacturer will have guidelines on the maximum allowable voiding. On the bottom, you see what happens with the vias left open. You get two problems: big voids and solder on the underside of the PCB.

Certainly there are some applications where this doesn't matter. That's why there is a second choice: "live with a bunch of voids and slopped solder." If you can't live with voids and solder slop, you have to bite the bullet and pay the extra for a PCB with filled vias. Board houses that do this have a variety of materials to use including copper, electrically conductive epoxy and thermal conductive epoxy.

Duane Benson
Please sir, may I have some more voids?
No! No voids for you!

 

Embedded at the Airport

I'm traveling to Phoenix today. Or, allegedly, I'm traveling to Phoenix today. The plan was to drop in to the office, do some work and print some things out for the trip, which I did. Then off to the airport. I left a little early in case traffic was bad or security was slow, but neither was the case and I ended up at my gate a full hour before my flight.

I'm not going to Phoenix for personal reasons. It's a business trip. I can't tell you what the purposes is. It's a bit of a secret. Not an interesting secret though. Not like I'm getting a sneak peak at a new chip or anything. But I am bringing some of my demo  boards down. LIke this one, and this one. Plus a Beagleboard that we assembled a while back and one more demo that I'll have at the ESC show later this month. Trust me though. This secret isn't anything of interest. Okay, it's of interest to me, but that's all.

Anyway, as the time ticked down and past my boarding time, I started to get nervous. The original plan was to take a United flight to LA, leaving here at 2:48, and have about a half hour to get to my connection and land at PHX at 7:08 pm.

Tic tock. Tic tock

Starting at our boarding time of 2:20, they regularly announced that there was a little mechanical delay. At some point, I inquired about my connecting flight in LA that I was now going to miss, but they moved me to a 9:00pm flight from LA to Phoenix. Ugh. Not long after that, they announced that the plane needed a part that had to be flown in from Salt Lake. Double Ugh.

Fortunately they were kind enough to put me on a direct flight, on US Air, leaving at 6:00 and arriving in Phoenix at 8:30.At 4:30, hour 3 at the airport, I was paged back to my original gate - on the other side of the airport. I ran back over there, planning on doing my best to talk them out of getting me baPhoenix window (Medium)ck on some double hope that would have me arriving at midnight. As it turns out, they had originally sent me down to US Air without a ticket and they were paging me back to pick it up. That was a cause worth hoofing it from oe side of the airport to the other and back.

Coming into Phoenix, we were delayed a bit for landing. I seems a dust storm had come up and put the airport into Instrument conditions. You know it's an interesting landing when the first thing the crew announces over the PA after touchdown is: "how was THAT for a landing" and the passengers all cheer.

Duane Benson
If this were on Twitter, my post would be: "I saw a cactus."

And Another Footprint Thing

Footprint wrong zero When you are creating a footprint in your favorite CAD program, or reusing someone else's footprint, double check the zero orientation. This post discusses the IPC-7351 specified zero rotation orientation.

This picture on the left shows a library component with the improper zero rotation orientation. Your centroid file will never be correct if you start from the wrong point.

IPC-7351 states that the LED should be oriented horizontally and the cathode (pin 1) should be to the left. Obviously, vertical and cathode up is not the same thing as horizontal and cathode left. If it's obvious, why do I feel the need to state it? I don't know. I just do.

Duane Benson
Red is gray and Yellow white
But IPC decides which is right

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