Screaming Circuits: June 2011


Family Reference

I've written a bit about reference designators here and there. There are a few more factors that we run into now and then. Take the family panel. In case you aren't familiar with the term, it means that you have several different designs laid out into in one panel, as opposed to multiple copies of the same design in one panel.

Using a family panel can be a convenient way to deal with a multi-board design and can sometimes save a bit of money. Just a caution, though. Make sure to check with your fab house first. Some don't like family panels and some won't separate them for you. If you do have them separated prior to assembly, either at the fab house or by you, then you don't have any reference designator worries.

S 065 My-9 600 If you leave them in the panel and wish to have them machine assembled, it can get a bit more complex though. "Why?", you say. I'll tell you why. Generally, most people start at "1" for each new design. i.e. "D1, D2, D3... R1, R2, R3..." If the boards go into the machine independently, that's no problem. However, if you send the panel into a smt assembly robot, it may very well see that as your board having multiple D1's, R1's, etc. That would be rejected as an error in most cases.

If you are using the family panel approach, don't restart your numbering when you move to another one of the designs that will be in the panel. Either continue on from the last number in the prior design, add in a hundred's, with each design getting a different hundred's number or add a unique suffix on each board.

  1. Wrong way: PCB1: "R1, R2, R3, R4, C1, C2". PCB2: "R1, R2, R3, R4, C1, C2".
  2. Right way: PCB1: "R1, R2, R3, R4, C1, C2". PCB2: "R5, R6, R7, R8, C3, C4".
  3. Right way: PCB1: "R101, R102, R103, R104, C101, C102". PCB2: "R201, R202, R203, R204, C201, C202".
  4. Right way: PCB1: "R1A, R2A, R3A, R4A, C1A, C2A". PCB2: "R1B, R2B, R3B, R4B, C1B, C2B".

There are a lot of ways to do this. Just make sure that no reference designators are repeated from one board design to the next. I prefer method #3 myself.

Duane Benson
Is it immediate or extended? Does it matter?

Favorites

What's your favorite MCU package and why?

  • The DIP is big and easy to use. You can stick it in a breadboard (wireless or soldered), a socket or easily hand solder it. But, it tends to be more expensive and takes up more real estate.
  • SOIC is a good step down in size. It can be machine soldered. It's big enough that most people can hand solder in a pinch. But, as an SMT, I'm not sure it has much purpose anymore. If there's an SSOP available for the same part, why would you take the bigger SOIC package?
  • SSOP are nice and small so that, unless you are really tight on space, they'll do just fine. They aren't really any more difficult to layout than and SOIC. If you do need to hand-solder, this package is probably too small. Being smaller with everything else being equal, it might have more issues with heat dissipation than the bigger part or a smaller one with a heat slug under it.
  • QFP - these are just lie either an SOIC or SSOP, but with leads on four sides.
  • BGAs are really compact and and do a good job of keeping signals close to the PCB and to bypass caps. They can be a challenge to layout though. Many will require upping your layer count. The really fine pitch BGAs may require expensive PCB features such as blind or buried vias. CSP and WSP BGAs can be more difficult to handle because of their small size. Breathing on them wrong can toss them around like dust.
  • QFN and DFNs are somewhat newcomers to the scene. The package can lead to some very tiny components. It's great for signal cleanliness and the heat slug underneath can dissipate (with proper layout) a lot of heat. But, QFNs and DFNs seem to garner the most layout problems. Careful use of thermal vias is critical for maximum performance, but you either have to use expensive techniques, such as filled and plated vias, or you have to rationalize and get around some nearly mutually-exclusive requirements.

Yeah. They all have their pluses and minuses. Fortunately, with proper board design, our SMT machines can place all of the these types all day long without breaking a sweat. All the SMT designs, that is. We do hand place the DIPs. What's your preference?

Duane Benson
All we are is BGAs in the wind

Via Current Capacity

Over on the Circuits Assembly blog, Michael asked a question about my Via in Pad Myth #5. He asked:

"I have a question about vias. I have seen charts on the current carrying capacity of traces, but what about vias?"

That's a good question. I've heard that you first need to know the thickness of the via wall. Then, once you know that, you can calculate the trace-width equivalent for the via by using the formula for the circumference (diameter X pi ). For whatever number that gives you, compare the closest smaller trace width.

Via cross section My related questions to all of you PCB fabrication gurus out there are:

Since vias are not created in the same way as the trace plating is, can that simple formula be used? While the trace copper is laminated onto a nice smooth PCB surface, the vias are typically created by deposition of copper dust in the via and then electroplating more copper. Then the surface finish is applied to all of the exposed metal. The via walls would generally be rougher than the flat substrate surface. Does that have an impact on the current capacity of a via?

Further, since airflow will be somewhat restricted in a via relative to a surface, should the via effective width be compared to an internal trace instead of an exposed surface trace? Should it be a compromise between the two?

If you look closely at this via cross I pulled from Wikipedia, you can see that the via wall looks to be thinner that the traces. You'll have to make sure that your board fab house can give you an accurate thickness of the via wall.

Duane Benson
If you know the via current capacity, can you calculate the past and future capacity?

Via-In-Pad Myth #5.A

I received a couple of good questions on my prior post about vias in QFN or QFP pads:

"I have a few questions about the second photo. The thermal vias in the center are masked over, doesn't this make it difficult to get uniform solder reflow on this pad? Also, what about the height differences due to the solder mask? Finally, what would the paste mask look like for this part?"

The part I used for the illustration is a QFP, but the same would go for QFNs also. All of the issues in question are somewhat more critical with QFN parts.

First, having the thermal vias masked over does make solder uniformity more difficult. The best option is to have the vias filled and plated over at the PCB fab house. That can be more expensive than is practical Padinvia_alt w stencil in many case though, so mask is still frequently used. A smaller mask size, 100 - 125 microns bigger than the via, is preferred to the larger mask are here, but this technique is used when registration is a concern. Again, it can be a cost issue. With a properly segmented mask, as illustrated on the right, reasonable solder deposition can be achieved.

Height isn't much of an issue with QFP parts, but can be with QFNs. Again, when the mask is properly segmented, height issues will be effectively mitigated.

Duane Benson
Stanley Yelnats doesn't like vias.

Random Via-In-Pad Myth #5

Myth #5: When you need thermal vias, more is better, bigger is better

Hmmm. Logically, this would seem to be the case. There are limits though; especially if you want a reliably assembled product. Older parts with heat slugs easily accessible for bolting on heat sinks didn't have this issue. Just bolt on a piece of metal and maybe blow a fan across it. It's different with a lot of the new, Padinvia smaller surface mount packages. Many have a heat slug on the bottom which requires carefully placed thermal vias to a copper pad on the underside of the board.

An extreme case of flooding the land with vias can be seen in this illustration here on Padinvia_alt the left. In terms of assembly, you can hack this together for a prototype, but it'll never fly in a production environment.It would be much better to use fewer smaller vias and have the center land covered with solder mask except where the metal on the chip is exposed, as in the illustration on the right.

Duane Benson
Place one carrot seed in each via and cover it with planting soil

Loopy Ground Loops

A while back, I posed a question about using flood fill (AKA copper pours). I've been reading a lot about ground loops lately which brought me back to that original question.

LED scroll ground plane Some people suggest segmenting your ground plane between analog and digital sections. Some people suggest segmenting the ground plane for individual critical ground return paths. The follow on to my original question is: On non-exotic designs does segmenting ground planes really help? There's actually two questions, with the second being: At what clock speed does it make sense to start worrying about issues caused by ground return paths / ground loops? There are probably more questions. Those are just the two rattling around in my head at the moment.

Interestingly, though, when I wrote the original post, there didn't seem to be a clear "most common" between pour and no pour PCBs. Today, I'd have to say that the majority of designs we see here at Screaming Circuits do use flood-fill ground planes, either internal or external.

Duane Benson
You can solve ground and noise problems by just not hooking up power

Package Variants

Cap under connector footprint Here's another issue we see from time to time involving the old, familiar, 0.1" pitch headers. Break away header When initially laying out the board, the footprint for the break-away header is used. It's small and easy to use. The headers are cheap and easy and you don't need to stock a bunch of different pin-counts.

That's all fine and dandy until the next rev of the prototype when you decide to change to a shrouded header for the additional reliability and pin protection afforded by it. When making that change, don't forget that the footprint with the shroud may very well be bigger than the break-away footprint.

Shrowded header In this particular case, it wouldn't have mattered except for the capacitor that ended up under the shrouded header.

Duane Benson
Get out of my cap's space, man

And The Race Goes On

AUP package The race for the smallest part is still going strong. That and the fact that basic logic gates are still with us is affirmed quite well with a new set of chips from NXP. The 74AUP2G00 is a dual two-input NAND gate in a no lead XSON8 package at just 1 mm x 1.35 mm. That's not the scary part. The scary part is the lead pads under the part are 0.15 mm wide and just 0.35 mm pitch center to center. That's 5.9 mils and 13.8 mils respectively. The gap between the pads is 0.2 mm (7.8 mils).

To put that in a little bit of perspective, an 0201 passive component is 24 mils x 12 mils. An 01005 is 16 mils x 8 mils.

Above right is a land pattern for the part with an 0201 bypass cap next to it. The trace going from the pin to ground (Pin 4) is an 8 mil trace. The trace going to VCC (pin 8) is six mils. The via is a pretty standard 24 mil via. As you can see, an eight mil trace and space isn't going to do for a board with this size of part on it. Six mil is really even a bit too big.

Duane Benson
La de da de de, la de da de da

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