DB25 With Issues
Take a look at this footprint. We're looking at the solder-side of a DB-25 connector footprint. Given all of the smt and HDI (High Density Interconnect) we see these days, this looks pretty primitive; like it could be straight out of 1979 or something. But it is a recent PCB design. Some of those good old-standard parts still have a place in today's world.
However, old or new, issues can still pop up. So, just what do you see wrong with this one? There are at least two pretty obvious, and a third issue that may be a little open to debate.
Duane Benson
What's wrong with this picture?
1. The solder mask is supposed to be 2 or 3 mils larger than the pad and definitely not cover the pad. There are no solder joints. This is a CAD library padstack construction error. After plugging and unplugging the mating connector a dozen times, this connector will come loose from the PCB.
2. The DRC trace to pad spacing rules seem to be smaller than the trace width. If the pad solder mask was swelled 3 mils it could have caused pad to trace solder bridging.
3. Avoid placing vias in-between rows of connector pins. The via is also directly under the connector and hopefully there are no metal parts in the connector that are near the via that will cause a short circuit.
4. I always use tear-drops on my through-hole trace to pad entries, especially connectors. Notice the drill hole in the via is offset toward the trace. A tear-drop would have reinforced the connection.
Any PCB fabrication shop with a front end CAM system would have caught all of these issues, but the PCB designer should have also been aware. Looks like these issues slipped by several people in the process.
Posted by: Tom Hausherr | March 31, 2010 at 01:44 PM
I'd place the via between pins only as a last resort.
Wether or not the traces are 'too' close to the pads, they are certainly closer than they have to be.
Maybe I'm old fashoned, but on a small trace entering a pad, especially one that might be subject to mechanical stress, I'd add some teardropping.
Posted by: Gary Crowell | March 31, 2010 at 01:23 PM
no.1 I would not place vias between connector pins
no.2 as Tony said, the soldermask seems to cover the pads
no.3 the zig-zag effect on traces can produce trace defects, so E-test might fail on some of the boards
Posted by: Florin | March 29, 2010 at 12:57 PM
Appears as though the soldermask is covering the pads. Cannot tell is this is a manufacturing error, soldermask offset.
The traces run closer to some of those pads then I would allow... perhaps that is debatable.
Tony
Posted by: Tony Rolando | March 29, 2010 at 11:39 AM