Screaming Circuits: October 2007

PBGA and counterfeit parts

Commonly held wisdom tells us that "PBGA" is an acronym for "Plastic Ball Grid Array." The "Plastic" refers to the material used to encase the silicon substrate and serve as the mechanical support for the component. In most cases, we have found this to be the case and we are very well versed at handling this type of component, be it a lead-free RoHS or a traditional leaded part.

However, we have recently received word of a small counterfeit ring operating out of the dirt patch behind a garage, right next to an old Ford, up in Kelso, Washington. The perpetrator and his crew aren't necessarily high-tech folks, but they are avid duck hunters and as any bird hunter well knows, the use of lead shot for upland game fowl has been banned for several years now. According to statements made by him and his little brother, lead has a greater reach then does the steel shot used in shotgun shells today.

Pbga_1_2The counterfeit ring has been scraping the lead balls off of BGA parts and replacing them with miniature pumpkins, resulting in PBGA (Pumpkin Ball Grid Array) or just Pumpkin Grid Array for short (click the photo for a larger view). They then fill their shotgun shells with the lead balls, grab a half-rack and go hunt'n.

The main problem with the counterfeit components is that pumpkins tend to not conduct electricity as well as lead solder or SAC solder balls do. This disadvantage is slightly offset by the wonderful pie-like aroma that emanates from our reflow oven when boards with these parts are processed.

During pumpkin season, we request that you inspect your plastic BGA parts for pumpkin contamination, or at least send whipped cream along with your parts kit. Everyone knows Pumpkin pie is better with whipped cream.

Duane Benson
let not the sands of time get in your lunch

The Evils of Parts Libraries

Well, maybe "evil" is too strong of a word, but it sometimes seems fitting, given the amount of grief caused by parts libraries in CAD packages. Sometimes it's because the part isn't in the library. Sometimes it's because the solder paste stencil pattern would lead to poor soldering. Sometimes the part size is just wrong.


Here's a case where the part outline didn't quite match the package. The designer wanted to get bypass caps in as close to the BGA pins as is possible - that can be very important with many components these days, especially RF and high-speed parts.

Unfortunately, the part outline in the CAD library did not match the actual outline of the part. I don't know why. Maybe this is a functionally equivalent substitution from another manufacturer. In any case, it speaks to the value of verifying things like actual part dimensions before sending the board out for fab.

Duane Benson
actual size may vary

Lead-free pcb finishes

Sc_rohs_on_grey_100 RoHS became Euro-law more than a year ago but it seems like the Industry still hasn't agreed on what an ideal RoHS pcb finish might be. Part of the problem is that we aren't just dealing with RoHS issues these days. The advanced packaging just adds to pcb-grief.

More and more components are showing up in QFN, micro BGA and wafer-scale packages. All of these are more sensitive to surface flatness. Lead-free HASL (Hot Air Surface Leveling) is decent for solderability, but it can have a bumpy surface which those little packages don't like.

ENIG (Electroless Nickle Immersion Gold) gives a nice flat and level surface with good solderability and high resistance to tarnish. But if the processing at the board fab house isn't spot-on, it can suffer from black pad problems - especially with BGA and QFN packages. Silver, again has a flat surface and good solderability, but it can corrode in salty or high sulfur environments (like near the coast or in industrial facilities) and is  susceptible to tarnish and oxidation.

I ran across an interesting article on the subject in the online Lead-Free Magazine. The first half is interesting but mostly about pot soldering. If you don't find that interesting, scroll down to about paragraph 12 for their take on the board surface issue.

Duane Benson
Warning: Plot complication
Warning: Plot complication
Warning: Plot complication

Degree in Robotics Engineering

I have a lot of interest in robotics and have posted a bit on the subject before. Last month, at the Embedded Systems Conference, in Boston, I ran across a professor from Worcester Polytechnic Institute.

Ma00146cworcesterpolytechnicinsti_2 I wasn't familiar with the institution, but apparently it's been around since 1865. I don't think they had too many robots back then, but recently, they started offering a four-year "Robotics Engineering" degree program.

It would have to be a pretty interesting program, combining, mechanical, electrical and software. According to the professor I spoke with, this is the first four-year robotics engineering degree program in the nation. Very cool. Check it out.

Duane Benson
Exterminate! Exterminate!

Sometimes You Need the Hole

Plugged_lead_holeI've spent so many posts discussing how to avoid putting vias, open holes, in your pads. Sometimes though, the opposite happens. Here's just one more reason to take a good look at your layout before sending it off for fab and assembly.

I'm not sure how this happened and from the photo, I'm not really sure if it's a TO-220, TO-247 or ME-262 part. In any case, because the annular rings are so small, I suspect that it was a custom created library part. It's possible that an error was made when creating the component. More likely, I'd guess that an SMT pad was manually put down on one leg to indicate pin one, and the CAD package or the board house ended up choosing the SMT pad over the hole.

It's a very odd looking thing though, without an easy solution. Just another reason for a good design check before sending the files out for board fab and before sending the boards out for assembly. It's possible that this would have looked okay in the CAD package, so a check of the boards before assembly could same some money and time even if it wasn't caught before fab.

Duane Benson
Take me home, country roads


We like to give tours here at Screaming Circuits. Unfortunately, we can't give too many tours because then we'd be spending all our time showing the place instead of building boards. Also, most of you don't live here so you can't get by to drop in.

Still, even if we can't have you all over for a tour and a soda, we want you to get to know us a bit better. For the last eight weeks in a row, we've delivered 100% of your assembly jobs on time. We've had 100% on-time delivery in 12 of the last 13 weeks. That kind of performance is due in large part to the customer service folks whom you speak with on the phone and via email.

Here's a brief introduction to a couple of them.

Now you know a couple of the people who are working for you in here. And you know why some of those packing peanuts might be a little squished. Don't worry. They were sealed in protective plastic at the time.

Duane Benson
We're still afraid of bears.


Don't do this! Friends don't let friends wire wrap.


Duane Benson
Which wire? The blue one.

Prototyping with Multi Layer Boards

a guest post by Nolan Johnson of Sunstone Circuits (PCBexpress)

Over here at Sunstone Circuits, we’ve been tracking the increased use of a technique with which many of our PCB123 users have been prototyping. It’s an interesting development that also shows up in our conversations with PCB engineers at trade shows, customer sites, or whenever we find ourselves discussing prototyping techniques with designers using a wide variety of PCB layout tools.

What’s unique about this new technique is that designers are increasingly using multi-layer board designs throughout the prototype phase to shorten the initial design times and save project dollars in the long run.

Here’s how this approach works for many engineers:

  1. Rather than struggle for a couple weeks to squeeze their prototype design onto a two-layer board, designers are adding an internal layer or two to the prototype board. Expand the spacing between traces a just touch and let the auto-router do the work for you. This will drastically shorten the layout time spent on the prototype and potentially shaves a spin off the overall prototyping process by allowing you larger tolerances.
  2. The designers then get the boards assembled and validate the prototype’s core functionality. While the purchase price for the prototype’s bare board will be a bit higher, the saved labor costs that result by taking a week or so off the prototype layout process are much greater than the incremental fab costs.
  3. These designers tend to enter the production optimization phase ahead of schedule and under budget, leaving them valuable breathing room with which to optimize down to a production-ready two-layer board.

The benefits to the design team are as follows:

  • Shorter design time – less labor cost
  • Better DFM tolerances – reduced risk of shorts or design mistakes
  • Fewer prototype spins – saved budget dollars on boards and, more importantly, components & assembly labor

Large PCB design firms have been using this prototyping technique for a number of years now. It works well for designs in which there isn’t a lot of high-speed design, and where strict compliance is not a requirement.

So how does this all pencil? Let’s look at an example using some hypothetical numbers. As always, your specifics will be different than the ones in this example. Work the numbers with your specific data to estimate the savings you’ll see in your environment.

For the meantime, though, let’s assume:

  • layout designer costs you $100/day,
  • design takes 12 work days to lay out,
  • PCB bare boards cost $350 to fabricate,
  • $1,500 in parts and assembly costs to populate your board, and
  • a typical prototype process requires three spins.

Let’s also assume that the multi-layer technique results in a $500/order cost for PCB fabrication, reduces design time to four days, and cuts your spins down by one. The numbers roll up like this, resulting in a multi-layer prototype that’s actually 52% of the cost of the 2-layer approach, and requires 35% of the design days:


Now, for this technique to work well there are a few prerequisites. If only some of these conditions apply, your payoff may not be as noticeable. If none apply, you’re probably not a good candidate for this approach:

  • Your company accounts for staff labor as a part of the project cost. If you’re a hobbyist or an individual working on your own (no-cost) time, then this technique still works but is of more limited value.
  • Your prototype board will be optimized before production. If your prototype is likely to be used unchanged for production, your product will carry an ongoing incremental cost increase as a result of the multi-layer board. If you’re plan all along to optimize down to a two-layer configuration, then the 33 days you saved ought to give you plenty of time to get the optimization ‘just right’.
  • Your board will fit within the restrictions of a two-layer format once optimized. The first step is to assure yourself that you’ll be able to get your circuit to fit on your target production format before you even begin.

We’d love to hear from you on how this technique has worked for you on your designs. Drop a comment here, or email Sunstone at:

Top-ten Reasons for Via in Pad

Okay, so it's really just a top-seven. I hope you don't feel cheated. If you do, then go here and read more about via-in pad.

Now, here are the top-seven reasons for putting vias in pads:

#7.  Grounding the center flag pad on a QFN. All those little electrons might need a quick and easy way home - (or is it the holes that need a quick and easy way to go to work??)

#6.  Cooling the QFN center flag pad. If light can be both a wave or a particle, why not heat? All the little Kelvonic particles will run down the via and hide on the other side of the PCB. Kelvons are better than Photons because Kelvons have feet.

#5.  Greater BGA routing flexibility. Put the via in the BGA pad (make sure your board house fills it and plates over it) and you can run traces between the pads. Then your signals can have races on the traces.

#4.  Keep all that messy solder off the top side of your board. It's easier to inspect a pcb assembly, especially underneath a BGA, if all the solder gets sucked down through a via to the other side of the board. As long as the circuit doesn't actually need to work...

#3.  Promote tombstoning with small passive parts. Put a via in one pad on a small passive and take bets on whether the part will pop up like a tombstone in the other pad. Wyatt Earp can be PN# 478-1051-1-ND and Ike Clanton can be PN# 478-1055-1-ND. No unauthorized component substitutions, please.

#2.  Presents for friends and family of PCB fab company executives. Doing it right by filling and plating over costs money. As we say in the marketing bizz, that service is a "high-margin accessory". Of course, doing it wrong, costs even more money.

... and ...

The number one reason to put vias in pads is:

#1.  Get revenge on your manufacturing folks for all of those annoying documentation requirements they keep throwing at you.

Duane Benson
Via la Screaming Circuits!

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